differential clock buffer/driver ddr333/pc2700-comp liant cy2sstv857-27 rev 1.0, november 21, 2006 page 1 of 8 2200 laurelwood road, santa clara, ca 95054 tel:(40 8) 855-0555 fax:(408) 855-0550 www.spectralinear.co m features ? operating frequency: 60 mhz to 200 mhz ? supports 266, 333 mhz ddr sdram ? 10 differential outputs from 1 differential input ? spread-spectrum-compatible ? low jitter (cycle-to-cycle): < 75 ? very low skew: < 100 ps ? power management control input ? high-impedance outputs when input clock < 10 mhz ? 2.5v operation ? pin-compatible with cdc857-2 and -3 ? 48-pin tssop package ? industrial temp. of ? 40 to +85c ? conforms to jedec ddr specification description the cy2sstv857-27 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. the cy2sstv857-2 7 generates ten differential pair clock outputs from one differ- ential pair clock input. in addition, the cy2sstv85 7-27 features differential feedback clock outputs and in puts. this allows the cy2sstv857-27 to be used as a zero-delay buffer. when used as a zero-delay buffer in nested clock tr ees, the cy2sstv857-27 locks onto the input reference and tr anslates with near-zero delay to low-skew outputs. block diagram pin configuration 32 5 6 1 0 9 2 0 1 9 2 2 2 3 4 6 4 7 4 4 4 3 3 9 4 0 2 9 3 0 2 7 2 6 3 2 3 3 y 0 y 0 # y 1 y 1 # y 2 y 2 # y 3 y 3 # y 4 y 4 # y 5 y 5 # y 6 y 6 # y 7 y 7 # y 8 y 8 # y 9 y 9 # f b o u t f b o u t # t e s t a n d p o w e rd o w n l o g ic p l l 1 3 1 4 3 6 3 5 f b in f b in # c l k c l k # a v d d 3 7 1 6 p d # 12 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 v s s y 0 # y 0 v d d q y 1 y 1 # v s s v s s y 2 # y 2 v d d q v d d q c l k c l k # v d d q a v d d a v s s v s s y 3 # y 3 v d d q y 4 y 4 # v s s 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 v s s y 5 # y 5 v d d q y 6 y 6 # v s s v s s y 7 # y 7 v d d q p d # f b in f b in # v d d q f b o u t # f b o u t v s s y 8 # y 8 v d d q y 9 y 9 # v s s cy2sstv857-27
cy2sstv857-27 rev 1.0, november 21, 2006 page 2 of 8 zero-delay buffer when used as a zero-delay buffer the cy2sstv857-27 will likely be in a nested clock tree application. for t hese applica- tions the cy2sstv857-27 offers a differential clock input pair as a pll reference. the cy2sstv857-27 then can lock onto the reference and translate with near-zero delay to low-skew outputs. for normal operation, the external feedbac k input, fbin, is connected to the feedback output, fbout. b y connecting the feedback output to the feedback inpu t the propagation delay through the device is eliminated. the pll works to align the output edge with the input refer ence edge thus producing a near-zero delay. the reference fre quency affects the static phase offset of the pll and thus the relative delay between the inputs and outputs. when vdda is strapped low, the pll is turned off an d bypassed for test purposes. power management output enable/disable control of the cy2sstv857-27 allows the user to implement power management schemes into the design. outputs are three-stated/disabled when pd# is asserted low (see table 1 ). note: 1. a bypass capacitor (0.1 f) should be placed as close as possible to each po sitive power pin (<0.2?). if these bypass capacitor s are not close to the pins, their high-frequency filtering characteristic will be can celled by the lead inductance of the traces. pin description pin number pin name i/o [1] pin description electrical characteristics 13, 14 clk, clk# i differential clock input . lv differential input 35 fbin# i feedback clock input . connect to fbout# for accessing the pll. differential input 36 fbin i feedback clock input . connect to fbout for accessing the pll. 3, 5, 10, 20, 22 y(0:4) o clock outputs differential outputs 2, 6, 9, 19, 23 y#(0:4) o clock outputs 27, 29, 39, 44, 46 y(9:5) o clock outputs differential outputs 26, 30, 40, 43, 47 y#(9:5) o clock outputs 32 fbout o feedback clock output . connect to fbin for normal operation. a bypass delay capacitor at this output will control input reference/output clocks phase relationships. differential outputs 33 fbout# o feedback clock output . connect to fbin# for normal operation. a bypass delay capacitor at this output will control input reference/output clocks phase relationships. 37 pd# i power down# input . when pd# is set high, all q and q# outputs are enabled and switch at the same frequenc y as clk. when set low, all q and q# outputs are disabled hi- z and the pll is powered down. 4, 11,12,15, 21, 28, 34, 38, 45 vddq 2.5v power supply for output clock buffers . 2.5v nominal 16 avdd 2.5v power supply for pll . when vdda is at gnd, pll is bypassed and clk is buffered directly to the device outputs. during disable (pd# = 0), the pll is powered down. 2.5v nominal 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 vss common ground 0.0v ground 17 avss analog ground 0.0v analog ground
cy2sstv857-27 rev 1.0, november 21, 2006 page 3 of 8 table 1. function table inputs outputs pll avdd pd# clk clk# y y# fbout fbout# gnd h l h l h l h bypassed/off gnd h h l h l h l bypassed/off x l l h z z z z off x l h l z z z z off 2.5v h l h l h l h on 2.5v h h l h l h l on 2.5v h < 10 mhz < 10 mhz hi-z hi-z hi-z hi-z off clkin t (phase error) fbin fbout t sk(o) yx yx yx t sk(o) figure 1. phase error and skew waveforms clkin t pd yx or fbin figure 2. propagation delay time t plh , t phl
cy2sstv857-27 rev 1.0, november 21, 2006 page 4 of 8 t c(n+1) yx t c(n) figure 3. cycle-to-cycle jitter pll fbin fbin# 120 ohm 120 ohm clk clk# ddr - sdram 120 ohm vtr vcp 0.3" = 2.5" = 0.6" (split to terminator) ddr _sdram represents a capacitive load ddr - sdram fbout# fbout output load capacitance for 2 ddr-sdram loads: 5 pf < cl< 8 pf figure 4. clock structure # 1 clk clk# ddr-sdram pll fbin fbin# 120 ohm 120 ohm ddr-sdram stack ddr-sdram stack 120 ohm vtr vcp 0.3" = 2.5" = 0.6" (split to terminator) ddr-sdram represents a capacitive load fbout# fbout ddr-sdram ddr-sdram ddr-sdram output load capacitancce for 4 ddr-sdram loads: 1 0 pf < cl < 16 pf figure 5. clock structure # 1
cy2sstv857-27 rev 1.0, november 21, 2006 page 5 of 8 6 0 o h m r e c e iv e r v c p v t r r t = 1 2 0 o h m o u t o u t # v d d q 6 0 o h m 1 4 p f 1 4 p f v d d q / 2 v d d q /2 v d d q figure 6. differential signal using direct terminat ion resistor
cy2sstv857-27 rev 1.0, november 21, 2006 page 6 of 8 absolute maximum conditions [2] input voltage relative to v ss :............................... v ss ? 0.3v input voltage relative to v ddq or av dd : ........... v ddq + 0.3v storage temperature: ............................... . ?65c to + 150c operating temperature:............................. ....... 0c to +85c maximum power supply: .............................. .................. 3.5v this device contains circuitry to protect the input s against damage due to high static voltages or electric fiel d; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to t his circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v ddq . unused inputs must always be tied to an appropriate logic voltage level (either v ss or v ddq ). dc electrical specifications (av dd = v ddq = 2.5v 5%, t a = 0c to +85c) [3] parameter description condition min. typ. max. unit v ddq supply voltage operating 2.38 2.5 2.63 v v il input low voltage pd# 0.3 v ddq v v ih input high voltage 0.7 v ddq v v id differential input voltage [4] clk, fbin 0.36 v ddq + 0.3 v v ix differential input crossing voltage [5] clk, fbin (v ddq /2) ? 0.2 v ddq /2 (v ddq /2) + 0.2 v i in input current [clk, fbin, pd#] v in = 0v or v in = v ddq ?10 10 a i ol output low current v ddq = 2.375v, v out = 1.2v 26 35 ma i oh output high current v ddq = 2.375v, v out = 1v ?28 ?32 ma v ol output low voltage v ddq = 2.375v, i ol = 12 ma 0.6 v v oh output high voltage v ddq = 2.375v, i oh = ?12 ma 1.7 v v out output voltage swing [6] 1.1 v ddq ? 0.4 v v oc output crossing voltage [7] (v ddq /2) ? 0.2 v ddq /2 (v ddq /2) + 0.2 v i oz high-impedance output current v o = gnd or v o = v ddq ?10 10 a i ddq dynamic supply current [8] all v ddq , f o = 170 mhz 235 300 ma i dd pll supply current v dda only 9 12 ma i dds standby supply current pd# = 0 and clk/clk# < 10 mhz 100 a cin input pin capacitance 4 pf ac electrical specifications (av dd = v ddq = 2.5v5%, t a = 0c to +85c) [9, 10] parameter description condition min. typ. max. unit f clk operating clock frequency av dd , v ddq = 2.5v 0.2v 60 200 mhz t dc input clock duty cycle 40 60 % t lock maximum pll lock time 100 s d tyc duty cycle [11] 60 mhz to 100 mhz 49.5 50 50.5 % 101 mhz to 170 mhz 49 51 % tsl(o) output clocks slew rate 20%?80% of vod 1 2 v/ns notes: 2. multiple supplies: the voltage on any input or i/o pin cannot exceed t he power pin during power-up. power supply sequenci ng is not required. 3. unused inputs must be held high or low to prevent them from floating. 4. differential input signal voltage specifies the d ifferential voltage vtr?vcpi required for switching , where vtr is the true input level and vcp is the complementary input level. see figure 6 . 5. differential cross-point input voltage is expecte d to track v ddq and is the voltage at which the differential signa l must be crossing. 6. for load conditions see figure 6 . 7. the value of voc is expected to be (vtr + vcp)/2. in case of each clock directly terminated by a 120 resistor. see figure 6 . 8. all outputs switching load with 14 pf in 60 environment. see figure 6 . 9. parameters are guaranteed by design and character ization. not 100% tested in production. 10. pll is capable of meeting the specified paramete rs while supporting ssc synthesizers with modulatio n frequency between 30khz and 50 khz with a down spread or ?0.5%. 11. while the pulse skew is almost constant over fre quency, the duty cycle error increases at higher fr equencies. this is due to the formula: duty cycle = t whc /t c , where the cycle time(tc) decreases as the frequency goes up.
cy2sstv857-27 rev 1.0, november 21, 2006 page 7 of 8 t pzl , t pzh output enable time [12] (all outputs) 3 25 ns t plz , t phz output disable time [12] (all outputs) 3 8 ns t ccj cycle to cycle jitter [10] f > 66 mhz ?75 ? 75 ps tjit(h-per) half-period jitter [10, 13] f > 66 mhz ?100 ? 100 ps t plh( t pd) low-to-high propagation delay, clk to y test mode on ly 1.5 3.5 7.5 ns t phl( t pd) high-to-low propagation delay, clk to y 1.5 3.5 7.5 ns t sk(o) any output to any output skew [14] 100 ps t phase phase error [14] ?50 50 ps notes: 12. refers to transition of non-inverting output. 13. period jitter and half-period jitter specificati ons are separate specifications that must be met in dependently of each other. 14. all differential input and output terminals are terminated with 120 /16 pf, as shown in figure 5 . ac electrical specifications (av dd = v ddq = 2.5v5%, t a = 0c to +85c)(continued) [9, 10] parameter description condition min. typ. max. unit
rev 1.0, november 21, 2006 page 8 of 8 cy2sstv857-27 while sli has reviewed all information herein for a ccuracy and reliability, spectra linear inc. assume s no responsibility for the use of any cir- cuitry or for the infringement of any patents or ot her rights of third parties which would result from each use. this product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critic al medical instruments, or any other applica- tion requiring extended temperature range, high rel iability, or any other extraordinary environmental requirements unless pursuant to additional processing by spectra linear inc., and expressed wr itten agreement by spectra linear inc. spectra line ar inc. reserves the right to change any circuitry or specification without notice. package drawing and dimension ordering information part number package type product flow cy2sstv857zc-27 48-pin tssop commercial, 0 to 70 c CY2SSTV857ZC-27T 48-pin tssop?tape and reel commercia l, 0 to 70 c cy2sstv857zi-27 48-pin tssop industrial, ?40 to +85c cy2sstv857zi-27t 48-pin tssop?tape and reel industria l, ?40 to +85c lead-free cy2sstv857zxc-27 48-pin tssop commercial, 0 to 70 c cy2sstv857zxc-27t 48-pin tssop?tape and reel commerci al, 0 to 70 c cy2sstv857zxi-27 48-pin tssop industrial, ?40 to +85c cy2sstv857zxi-27t 48-pin tssop?tape and reel industri al, ?40 to +85c 48-lead thin shrunk small outline package, type ii (6 mm x 12 mm) z48 51-85059-*b
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